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Cypress Semiconductor /psoc63 /PDM0 /DATA_CTL

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Interpret as DATA_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BIT_LEN16)WORD_LEN 0 (BIT_EXTENSION)BIT_EXTENSION

WORD_LEN=BIT_LEN16

Description

Data control

Fields

WORD_LEN

PCM Word Length in number of bits:

(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)

0 (BIT_LEN16): 16-bit

1 (BIT_LEN18): 18-bit

2 (BIT_LEN20): 20-bit

3 (BIT_LEN24): 24-bit
BIT_EXTENSION

When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. ‘0’: Extended by ‘0’ ‘1’: Extended by sign bit (if MSB word is ‘1’, then it is extended by ‘1’, if MSB is ‘0’ then it is extended by ‘0’)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data